A very helpful SD manufacturer's design engineer provided the following notes.
The information is provided "AS IS":
The actual read access time is Nac and has a minimum of 1 unit (1 unit = 8
clocks). It also has a maximum given in a equation form. After
you workout the equation, you will see that the maximum is 10xTAAC.
TAAC is typically 10ms. This makes the maximum read access time 10 x
10ms => 100ms.
For write, you multiply the R2W_FACTOR by the read access time.
R2W_FACTOR is 1:4. In other words, 4 X the read access time.
This will give us a maximum of 4 x 100ms => 400ms for write.
If your read or write exceeds the 100ms and 400ms respectively, then we have
an issue. If it is within the 100ms and 400ms, then no problem exists.
The 100ms & 400ms are timeouts. This basically says that it is
possible for a block read or write to take up to 100ms or 400ms respectively
. It does not mean that every block will be 100ms/400ms. You'll
see it is a lot faster than 100ms/400ms per block. You need to make
sure you're using multiple block read/write commands , maximum clock
frequency, and 32KB+ (64+ blocks) data sizes for your multiple block
Our cards will always write to erased sectors,
so doing an erase before write will not change anything.
The 100ms/400ms applies to the MMC cards and it
can vary depending on the card manufacturer. You should always read
the CSD register to get the actual TAAC, R2W_FACTOR and calculate your
timeouts for MMC cards. For the SD cards, this value is fixed to
100ms/250ms by the SDA for read/write.
Multiple block write does NOT necessary reduce
the delays. Multiple block write takes advantage of the card's
internal parallel writing/reading scheme. Typically the cards will
have internal block buffers that take multiple blocks of data and write them
in parallel or read multiple blocks in parallel. This speeds up the overall
read and write performance.
MMC and SD card has a built in controller that manages the internal NAND
memory. This controller runs many tasks including, wear leveling, ECC,
CRC, block management , etc ...Depending what the controller is doing when
you send the read/write command, the read/write time can vary between 0 to
maximum timeout. The MMCA and the SDA have timeout requirements for
the card manufacturers. This is a way to guarantee that after a
certain time the card will either complete the read/write task or return an
error. Therefore, even if you see cards with lower delays, there is no
guarantee that the delay will always stay low. The only guarantee you
have is the timeout values. This is what you should design your to so
that you meet the SDA and MMCA specifications.
I usually recommend 2x the maximum timeout
period. If you are looking at 40KB/s for write and the max timeout is
250ms, then your buffer should be around 20KB. If you have other
system/overhead delays not related to the card, then you have to increase
the buffer size.
Last update: 02/29/12